Data processing devices in conventional data processing systems often access an external peripheral device memory in the system, for example a memory. With external memory devices such as DRAMs, memory cycles often require more than one clock cycle for completion, and such memory cycles should preferably not be interrupted. This presents problems in some circumstances, such as when the data processing system is being operated in an emulation mode. For example, although the memory cycle should not be stepped through with an intermittent emulation step clock, it is nevertheless advantageous to use the step clock for stepping the data processing device through its operations. However, if the data processing device is being intermittently stepped by the step clock while a memory cycle is being performed using the normal system clock, then a synchronization problem can occur at the interface between the data processing device and the external memory.
It is therefore desirable to provide a data processing apparatus capable of compensating for synchronization problems of the type described above.
A data processing apparatus according to the present invention includes control circuitry connectable to a peripheral device for executing an access of the peripheral device, and data processing circuitry connected to the control circuitry for requesting the peripheral access. The control circuitry includes synchronizing circuitry for synchronizing the control circuitry with the data processing circuitry after completion of the peripheral access.